Present day electronic equipment, including processors and related devices, frequently requires transmission lines such as buses to provide high speed connections for passing signals between circuit elements. To this end, printed circuit boards (PCBS) and multiple chip modules (MCMs) can be manufactured with buses formed on one or more layers thereof to provide the desired high speed connections. Generally, a circuit element transmits a signal over the transmission line utilizing an output buffer to provide drive signals from the circuit element to the transmission line. Ideally, the output impedance of such output buffers is matched with a characteristic impedance of the transmission line. However, in reality, the output impedance of such output buffers is frequently mismatched with the characteristic impedance of the transmission line. The end result can be a significant decrease in signal integrity due to the mismatch, and a subsequent decrease in system performance.
As an example, in present processor systems using PCBs and MCMs, board manufacturers generally guarantee the boards to provide one or more buses typically having a variance of .+-.15% from a target value (e.g., 50-65 .OMEGA.). This means that the characteristic impedance of the buses can vary by 30% or more from lot to lot. In the past, buffers used with such buses have an output resistance referenced to an external resistor to try to set a target resistance. Inevitably, some products will be delivered with a significant impedance discontinuity between the buffers and the buses formed on the boards since, as noted above, the actual characteristic impedance of the board can vary by at least .+-.15% from the target value. This leads to a significant degradation of the signal integrity of the digital pulse signals provided to the buses by the buffers.
The problem of signal degradation caused by a mismatch between buffers and buses becomes worse as the speed of the buses is increased. One reason for this is that, as the speed of the buses increases, electrical delay on the buses becomes long compared with the edge rate of the digital pulses, resulting in significant reflections on the bus. A recent example of a high speed bus is the back side bus of the Pentium II (a registered trademark of Intel Corporation) processor, which presently runs faster than 200 MHz. At such high bus speeds, it is necessary for the impedance match between the output impedances of the buffers and the characteristic impedance of the buses to be as close as possible.
One solution to this problem is simply to provide better quality control of the characteristic impedance of the bus or buses formed on substrates such as PCBs or MCMs to reduce the variation from lot to lot. Unfortunately, this approach significantly increases the overall cost of the boards, which, of course, increases the overall product cost. Therefore, a significant need exists for an approach to minimize the amount of mismatch between buffers and buses without having to significantly increase the cost of manufacturing the boards.